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Toolbox for Real-time Implementation of MPC for Power Electronic Systems
In this project, you will first analyse an implemented quadratic program (QP) solver using Intel high-level-synthesis (HLS) tool and develop an optimization routine to compare the performance considering hardware resource constraints.
Keywords: Model Predictive control, MPC, QP, FPGA, HLS
At HPE, model predictive control (MPC) is investigated as an alternative
control method for power electronic systems since converters with MPC
can achieve a fast dynamic behavior and incorporate system constraints.
The challenging part is that an optimisation problem has to be solved with
limited resources in embedded systems within every sampling interval in
real-time, which is typically very short in power electronic systems (range
of a few μs).
In this project, you will develop a toolbox enabling a rapid realtime
implementation of MPC based on implemented quadratic program
(QP) solvers using the Intel high-level-synthesis (HLS) compiler. The
toolbox will execute an optimization routine to compare the performance
considering hardware resource constraints and verify the implementation
through FPGA-in-the-loop experiments.
At HPE, model predictive control (MPC) is investigated as an alternative control method for power electronic systems since converters with MPC can achieve a fast dynamic behavior and incorporate system constraints. The challenging part is that an optimisation problem has to be solved with limited resources in embedded systems within every sampling interval in real-time, which is typically very short in power electronic systems (range of a few μs). In this project, you will develop a toolbox enabling a rapid realtime implementation of MPC based on implemented quadratic program (QP) solvers using the Intel high-level-synthesis (HLS) compiler. The toolbox will execute an optimization routine to compare the performance considering hardware resource constraints and verify the implementation through FPGA-in-the-loop experiments.
Min Jeong, ETL F14, jeong@hpe.ee.ethz.ch
Min Jeong, ETL F14, jeong@hpe.ee.ethz.ch
30% Coding
50% Implementation
20% Simulation
30% Coding 50% Implementation 20% Simulation
Interest/basic knowledge in coding and FPGA,
Working language: English
Interest/basic knowledge in coding and FPGA, Working language: English